As the mobile device market mushroomed with the development of multifunctional smartphones, cellular communication complexity has increased accordingly. It is now conventional for a radio front end of a mobile device to cover as many as ten or more frequency bands. The radio front end thus requires multiple power amplifiers, diplexers, low-noise amplifiers, antenna switches, filters, and other radio frequency (RF) front end devices to accommodate the radio signaling complexity. These various RF front end devices are in turn controlled by a host or master device such as a radio frequency integrated circuit (RFIC). As the RF front end complexity increased, the need for a standardized protocol to control the many different devices lead to the development of the Mobile Industry Processor Interface (MIPI) RF Front End Control Interface (RFFE) standard.
The RFFE standard specifies a serial bus that includes a clock line and a bidirectional data line. Through the RFFE bus, an RFFE master device may read from, and write to, registers in a plurality of RFFE slave devices so as to control the RF front end devices. The read and write commands are organized in the RFFE standard into protocol messages that may each include an initial sequence start condition (SSC), a command frame, a data payload, and a final bus park cycle (BPC). The protocol messages include register commands, extended register commands, and extended register long commands. The protocol messages may further include broadcast commands. The register, extended register, and extended register long commands (three types of commands) can all be either read or write commands. With regard to the three types of commands, the registers in each of the RFFE slave devices are organized into a 16-bit wide address space (0x0000-0xFFFF in hexadecimal). Each of the three types of commands includes a command frame that addresses a specific RFFE slave device as well as the register address. A command frame in the register command (register command frame) is directed to the registers in the first five bits of an address space (0x00-0x1F) such that only five register address bits are needed. The register command frame is followed by an 8-bit data payload frame. In contrast, an extended register command frame includes eight register address bits and may be followed by up to 16 bytes of data. Finally, an extended register long command frame includes a full 16-bit register address so it can uniquely identify any register in the addressed RFFE slave device. The extended register long command frame may be followed by up to eight bytes of data.
Each of the commands begins with a unique sequence start condition (SSC) that is then followed by a corresponding command frame, some number of data frames, and finally a bus park cycle (BPC) to signal the end of the command. The latency involved with transmitting any of the commands thus depends on the number of bits in its various frames as well as the clocking speed for the RFFE clock line. Under the RFFE protocol, each bit of a transmitted frame corresponds to a period of the clock since the transmission is single data rate (SDR), which corresponds to one bit per clock cycle. For example, an SDR results from transmitting a bit responsive to each rising edge (or to just the falling edges) of the clock. The maximum clocking speed is 52 MHz in the RFFE v2 specification. This clocking rate has increased relative to previous versions of the RFFE protocol and is associated with increased power consumption. Each of the three types of RFFE commands—extended register, extended register long, and register—may be either a read or a write command.
On the RFFE bus architecture, as well as a system power management interface (SPMI) bus architecture, a particular command such as a Register-0 Write command provides a low latency technique for a bus master device to write 7-bit data at a fixed location (address: 0x0000, i.e., Register-0) of an addressed slave. While an existing Register-0 Write datagram may facilitate the sending of 7 bits of data to a fixed location (address: 0x0000) of a targeted device with minimal latency, emerging applications in developing technologies (e.g., 5G) demand more than 7 bits of data to be sent to a location of choice within an entire 64K register space, while improving latency over existing register-write techniques.
However, no such technique currently exists. Sending 8 bits of data or multiple bytes of data to any arbitrary location within the entire 64K register space requires the use of conventional register-write techniques and does not improve upon latency reduction. Accordingly, there is a need in the art for a novel technique that extends the data transportation capability of the Register-0 Write command in the entire 64K register space while maintaining full backward compatibility with legacy RFFE and SPMI devices.